1. Field of the Invention
The present invention relates to a process for producing a semiconductor device by using a crystalline semiconductor thin film. The semiconductor device of the invention includes not only a single device, such as a thin film transistor, but also an electronic apparatus having a semiconductor circuit comprising a thin film transistor, a liquid crystal display device typically using an active matrix substrate, and another electronic device equipped with an image sensor, such as a personal computer and a digital camera.
2. Description of the Related Art
A thin film transistor (TFT) is used in various integrated circuits, and because a TFT can be produced on an insulating substrate, such as glass and quartz, it is suitable as a switching device of a matrix circuit of an active matrix type liquid crystal display device.
As a semiconductor layer of a TFT, an amorphous silicon film and a polycrystalline silicon film are generally employed. In order to constitute a driver circuit of a matrix circuit with a TFT, a polycrystalline silicon film having a high mobility must be used as the semiconductor layer. In general, in order to form a polycrystalline silicon film used as the semiconductor layer, an amorphous silicon film is firstly formed, and then the amorphous silicon film is subjected to heat crystallization, in which a heat treatment is conducted, or laser crystallization, in which excimer laser light is used for irradiation.
At the present time, the upper limit of the process temperature for the crystallization is demanded to be about 600xc2x0 C. depending on the heat resistance of a glass substrate used in the active matrix substrate. Due to the use of a low crystallization temperature, a long period of time of 20 hours or more is required for the heat crystallization.
The laser crystallization technique using an excimer laser is a technique that realizes a process of a low temperature and a short processing time. Because the energy of excimer laser light is absorbed and converted into heat at a very surface of the amorphous silicon film of about 10 nm, an energy equivalent to heat annealing at about 1,000xc2x0 C. can be applied to the amorphous silicon film in a short period of time without giving any heat influence to the substrate, and therefore a semiconductor film having a high crystallinity can be formed.
As a structure of a TFT, a bottom gate type (typically a reverse stagger type) and a top gate type (typically coplanar type) are typically known. In the bottom gate type one, a gate wiring (electrode), a gate insulating film and a semiconductor layer are accumulated in this order on a substrate, whereas in the top gate type one, which is the reverse of the bottom gate type, a semiconductor layer, a gate insulating film and a gate wiring (electrode) are accumulated in this order.
A process for producing a reverse stagger type TFT using polycrystalline silicon will be briefly described with reference to FIGS. 18A to 18D. FIGS. 18A to 18D are cross sectional views along the channel length (gate length).
A metallic film having a thickness of from 300 to 500 nm comprising, for example, Cr or Ta is formed by sputtering method on a glass substrate 1, and is patterned into a tapered shape to form a gate wiring 2. A gate insulating film 3 having a thickness of from 100 to 200 nm comprising, for example, SiNy (silicon nitride) or SiO2 (silicon oxide) is then formed by a CVD method. An amorphous silicon film 4 having a thickness of from 50 to 100 nm is then formed by a CVD method. (FIG. 18A)
Crystallization is conducted by irradiation with excimer laser light to form a polycrystalline silicon film 5. (FIG. 18B)
The polycrystalline silicon film 5 is patterned to form a semiconductor layer 6. Impurities to be a donor or an acceptor are then selectively added to the semiconductor layer 6 to form a source region 6S, a drain electrode 6D and a channel-forming region 6C. (FIG. 18C)
An SiO2 film is then formed as an interlayer insulating film 7 by a CVD method. A contact hole is formed in the interlayer insulating film 7, and a source electrode 8 and a drain electrode 9 are formed. (FIG. 18D)
In the production process of a reverse stagger type TFT using polycrystalline silicon as shown in FIGS. 18A to 18D, because the film thickness of the gate wiring is about from 300 to 500 nm, whereas the film thickness of the gate insulating film is from 100 to 200 nm, unevenness is formed on the surface of the amorphous silicon film 4 as reflecting the shape of the gate wiring 2.
In the laser crystallization, it is general that excimer laser light is shaped into a line-shaped beam or a rectangular beam, and the beam is used for irradiation by scanning. However, because of the unevenness on the surface of the amorphous silicon film 3, the focal point of the beam is different at each position on the surface, and thus energy to be applied to the amorphous silicon film 3 becomes different at each position. Because it is substantially difficult to change the focal point of the beam to comply with the unevenness, unevenness in crystallization occurs in the polycrystalline silicon film 5 due to the deviation of the focal point of the laser light. The unevenness in crystallization causes unevenness in threshold voltage of the TFT.
A TFT using polycrystalline silicon also has a problem that an off electric current is large. It is considered that the cause of the off electric current is that a voltage applied to the drain electrode 9 where the TFT is in an on state is concentrated at a coupling part of the channel forming region 6C and the drain region 6D, and an electric current leaks at the coupling part through a trap.
Furthermore, in a TFT using polycrystalline silicon, because the thickness of the gate insulating film 3 is from 100 to 200 nm, which is thinner than in the case of using amorphous silicon, there is a problem in coverage property of a step at an edge part of the gate wiring 2 (see FIG. 18D). Because SiNy and SiO2 are difficult to grow by a CVD method at the edge part 2a, the thickness of the gate insulating film 2 becomes small. Accordingly, there tends to occur at the edge part 2a that the gate wiring 2 and the semiconductor layer 6 form a short circuit; the threshold voltage is shifted by implantation of an electron or a hole to the gate insulating film 3; and electrostatic breakage of the gate insulating film 3 occurs. These phenomena become factors deteriorating the reliability of the TFT.
An object of the invention is to solve the problems described above and to provide, in a semiconductor device of a bottom gate type comprising a gate wiring, a gate insulating film and a semiconductor layer accumulated in this order, a structure that provides uniformity in laser crystallization, and a process for producing such a structure. Another object of the invention is to provide a structure of a semiconductor device of a bottom gate type, in which an off electric current is suppressed to increase the reliability, and a process for producing such a semiconductor device.
In order to attain the objects, the invention provides a semiconductor device comprising by accumulating a gate electrode formed on an insulating surface; a gate insulating film comprising an accumulated film comprising a flattening film comprising an insulating organic resin and an insulating inorganic film, formed to cover the gate electrode; and a semiconductor layer covering the gate insulating film, wherein the semiconductor layer comprises a crystalline semiconductor film.
The invention also relates to a process for producing a semiconductor device having the accumulated structure described above, the process comprising
a step of forming a gate wiring on an insulating surface;
a step of forming a flattening film comprising an insulating organic resin to cover the gate wiring;
a step of forming an insulating inorganic film in contact with the flattening film;
a step of forming a semiconductor film having an amorphous component to cover the insulating inorganic film; and
a step of crystallizing the semiconductor film having an amorphous component to form a crystalline semiconductor film.
The term gate electrode used herein means a point of intersection of the gate wiring and the semiconductor layer. The source/drain wiring and the source/drain electrode are the same relationship as that between the gate wiring and the gate electrode.
In the constitution described above, the step between the gate electrode and the gate wiring is filled with the flattening film, and thus the surface of the gate insulating film becomes flat. Therefore, the semiconductor film having an amorphous component can be formed on a flat surface, and thus the semiconductor film itself can be made as a flat film. As a result, when laser light is applied thereto, there is no difference in focal point in each position, and the crystallization can be conducted uniformly in comparison to the conventional technique.
The insulating organic resin film can be generally formed by a coating method, and the coated film is further excellent in step coverage property in comparison to the insulating inorganic film formed by a gas phase method such as a CVD method. Therefore, in the insulating resin film, since the organic resin film does not become thin at the edge part of the gate wiring, the short circuit between the gate wiring and the semiconductor layer and the insulation breakage of the gate insulating film, which has been described above, can be prevented, so as to increase the reliability and the stability of the semiconductor device.
Furthermore, because the organic resin film has a smaller dielectric constant than that of the insulating inorganic film, a parasitic capacitance can be made small even when the gate insulating film is an accumulated film.
Since the insulating inorganic film is formed by a chemical vapor phase method such as a CVD method or a physical vapor phase method such as a sputtering method, an amount of impurities mixed therein is smaller and the size of the impurities is smaller than in the organic resin film. Therefore, by using an accumulated film of the insulating organic resin film and the insulating inorganic film, the amount of pinholes in the gate insulating film can be decreased, and the interface state between the semiconductor layer and the gate insulating film can be lowered in comparison to the case where the semiconductor layer is formed on the organic resin film.
In the constitution described above, the semiconductor film having an amorphous component is an amorphous semiconductor film having no crystallinity or a semiconductor layer having crystallinity but containing substantially no crystalline particle having a size of an order of 100 nm or more, and specifically includes an amorphous semiconductor film and a microcrystalline semiconductor film. The microcrystalline semiconductor film is a semiconductor film comprising a mixed state of microcrystals containing crystalline particles having a size of from several nm to several tens nm and an amorphous phase.
More specifically, examples of the semiconductor film having an amorphous component include an amorphous silicon film, a microcrystalline silicon film, an amorphous germanium film, a microcrystalline germanium film and an amorphous SixGe1xe2x88x92x (0 less than x less than 1) film, and these semiconductor films are formed by a chemical vapor phase method, such as a plasma CVD method and a reduced pressure CVD method, and a physical vapor phase method, such as a sputtering method.
The thickness of the semiconductor film is about from 10 to 150 nm.